Multi-Project Wafer; MPW Shuttle Program Manager

Job Details

Multi-Project Wafer (MPW) Shuttle Program Manager

Intel Corporation

2 days ago – Be among the first 25 applicants

The world is transforming – and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings.

We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

As part of this team, you will help us grow our secure solution suite to meet U.S. Government requirements. The Intel Information Security organization is seeking a Multi-Project Wafer (MPW) Shuttle Program Manager. The candidate chosen for this role will manage a team of engineers working on design, architecture, and build secure classified infrastructure products to support USG operations.

• Lead and execute multi-project shuttles across multiple Intel technologies, ensuring timely delivery and alignment with customer requirements.
• Develop and implement risk mitigation strategies to manage shuttle execution challenges.
• Enhance onboarding processes for first-time customers and streamline document management for ease of access and understanding.
• Optimize and innovate strategies and BKMs for seamless execution of end-to-end Shuttle operations.
• Collaborate with and coordinate among multiple subject matter experts and cross‑functional teams, including Tape‑out, Frames, Fab, Die Prep, and Assembly teams, to ensure alignment and success in shuttle operations.
• Develop roadmaps and execute strategic objectives for future shuttle projects.
• Foster a customer‑first attitude by maintaining strong relationships and delivering high‑quality service.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

• US Citizenship.
• Ability to obtain and maintain an active US Government clearance (TS/SCI).
• Bachelor’s with 4+ OR Master’s with 3+ OR PhD with 1+ years experience and a degree in Engineering, Computer Science, or another STEM field of study.
• 3+ years experience of relevant experience in silicon design, engineering project management, semiconductor shuttle operations and/or a similar role.
• 3+ years experience risk management and operational planning.
• 3+ years experience project management skills.

• Active US Government Security Clearance.
• Bachelor’s with 6+ OR Master’s with 4+ OR PhD with 2+ years’ experience and a degree in Engineering, Computer Science, or another STEM field of study.
• Familiarity with shuttle operations and Fab manufacturing processes.
• Proven track record of enhancing operation excellence and working with cross‑functional teams.
• Prior working experience with MPW / Shuttle or test chip design tapeout desired.
• Proven track record of technical leadership and project execution management in the complete life cycle of a Silicon on Chip (SoC) or similar products from definition to design and tape‑out.
• Working fluency on process technology parameters, overall semiconductor manufacturing steps from design fracture through package assembly, process characterization, physical design rules/runset.
• Familiarity with database management for large, multi‑site design projects.
• Working experience s of interfacing with process, design, and design automation teams.
• Good understanding of leading‑edge process technologies, devices, and the interactions with circuit design.
• Familiar with SoC, CPU and custom (analog and digital) design styles, flows, tools, and methodologies.
• Famili…