External Technology Integration Engineer
Listed on 2025-12-21
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Engineering
Systems Engineer, Electrical Engineering, Manufacturing Engineer, Process Engineer
External Technology Integration Engineer
Join Intel's Elite Technology Integration Team and Shape Tomorrow's Computing Solutions! Are you a visionary engineer passionate about pushing the boundaries of semiconductor technology? Do you thrive on solving complex technical challenges while leading cross‑functional teams in a fast‑paced, innovation‑driven environment? Intel is seeking an exceptional External Technology Integration Engineer to spearhead the integration of cutting‑edge memory and foundry silicon technologies into our revolutionary EMIB and Foveros advanced packaging architectures.
This is more than just an engineering role—it's an opportunity to be at the forefront of semiconductor innovation, working with industry‑leading technologies like High Bandwidth Memory (HBM), LP DDRs and Si nodes while collaborating with world‑class internal teams and external partners. As our External Technology Integration Engineer, you'll drive critical technology milestones from concept to production, establishing the standards, design rules and specifications that will define the next generation of computing solutions.
Transform Technology. Lead Innovation. Make Your Mark.
Job Responsibilities- Lead the technical integration of external memory and/or foundry silicon technologies into Intel's advanced packaging platforms
- Drive comprehensive chip‑to‑package interaction (CPI) assessments across Si backend fab, bump, singulation, assembly, and test domains
- Qualify breakthrough foundry Si/memory technologies and establish innovative Si far back‑end and bump design rules
- Orchestrate complex technical programs with multi‑disciplinary stakeholders to deliver game‑changing results
- Define package performance specifications and achieve technology certification through strategic test vehicle design layout and data collections
- Pioneer research on materials and properties to solve complex CPI failure mechanisms
- Establish critical material and process specifications for foundries and contract assemblers
- Lead and influence both internal and external stakeholders towards desired direction and timely execution
- Provide succinct presentations to senior executive management team along with excellent verbal and written communication skills
- Bachelor's degree in Materials, Chemical Engineering, Chemistry, Physics, Mechanical Engineering with 6 years related field experience
- Master's degree in Materials, Chemical Engineering, Chemistry, Physics, Mechanical Engineering with 4 years related field experience
- PhD degree in Materials, Chemical Engineering, Chemistry, Physics, Mechanical Engineering with 2 years related field experience
- 2 years developing and qualifying microelectronic packaging processes for high‑volume manufacturing (OR)
- 2 years integrating complex packaging assembly components including design specifications, manufacturing processes, materials selection, and tooling requirements (OR)
- 2 years managing technical programs with demonstrated experience in:
- Technical planning and scheduling
- Program execution and monitoring
- Completion of packaging assembly process certifications
- 2 years managing external relationships including:
- Supplier process, material, and tool management
- Customer program management with committed delivery schedules
- Experience in various versions of 2.5D and 3D advanced package architectures in the industry, their fabrication processes/materials/tools and their interaction and driving yield improvement activities for these advanced package architectures.
- Extensive experience in conducting failure mode and effects analyses (FMEA), technical risk assessments (TRA) and statistical process control (SPC) analyses.
- Experience in defining a silicon‑package architecture through fit study, technical risk assessments along with design for yield (DFY) and design for reliability (DFR) considerations.
- Extensive experience in Si far‑backend fab processes, memory/packaging technology, memory silicon/package interactions, silicon and/or package debug verifications, structure property relationships and material characterizations.
- Experience in model‑based…
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