SoC Physical Design Engineer
Listed on 2025-12-31
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Engineering
Electrical Engineering, Systems Engineer
Job Details
Job Description: Do Something Wonderful! Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
WhoWe Are
The role is within Intel’s highly regarded Devices Development Group, headquartered in Portland, Oregon with additional sites in Penang, Malaysia, and Bangalore, India. Our bold purpose as a company is to ‘create world‑changing technology that enriches the lives of every person on earth’ and this role is instrumental in furthering our mission to shape the future of technology.
Who You AreWe are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world‑changing technology that enriches the lives of every person on earth, and this role is instrumental in furthering our mission to shape the future of technology.
Responsibilities- Perform physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
- Physical synthesis, floor planning, placement and route, clock tree synthesis with Synopsys and/or Cadence EDA tools.
- Multiple power domain analysis and handling using standard power formats UPF or CPF.
- Verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, noise analysis and structural design checking.
- Analyze results and make recommendations to fix violations for current and future product architecture.
- Participate in the development and improvement of physical design methodologies and flow automation.
- Drive performance optimization, including co‑optimization, work with process teams, to create best‑in‑class designs.
- Minimum:
Bachelor’s degree in Electrical Engineering, Computer Engineering or related field with 3+ years of relevant experience, or Master’s degree with 2+ years of relevant experience. - Preferred:
Experience in physical design using industry EDA tools. - Preferred:
Experience in Python/Perl/TCL programming languages. - Self‑motivated with strong problem‑solving skills.
- Excellent interpersonal skills, including written, verbal, and presentation communications.
- Attention to detail and organizational skills.
- Ability to work as part of a team and collaborate in a high‑paced atmosphere.
Experienced Hire. Shift: Shift 1 (United States of America). Primary location: US, Oregon, Hillsboro. Additional locations:
Business group:
The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. Position of Trust: N/A.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as benefit programs which include health, retirement, and vacation. Find more information about all of our amazing benefits here.
CompensationAnnual Salary Range for jobs which could be performed in the US: $ – $ USD.
Work ModelThis role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change.
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