Hybrid HW Design Engineer - Memory Interfaces & ASIC​/FPGA

A leading semiconductor company is seeking a talented HW Design Engineer to join their MCG team in Hillsboro, Oregon. This role involves RTL coding, design architecture, and customer delivery. Candidates should have expertise in System Verilog/Verilog, at least 5 years of logic design experience, and a BSEE. The company offers a hybrid work model and a competitive salary ranging from $106,900 to $198,500, alongside extensive benefits including medical coverage and a gym membership.
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