Senior Design Engineer – AI SoC Development

Job Details

Job Description:

Intel's AI SoC organization develops cutting‑edge products powering a wide range of AI applications, from edge devices to data center accelerators. If you are an engineer with strong technical and communication skills who thrives in a fast‑paced environment with abundant learning opportunities, you are the ideal candidate for this role. Join us to shape the future of AI hardware.

You will develop logic design, register transfer level (RTL) coding, and simulation for SoC designs while integrating IP blocks and subsystems into full chip SoC or discrete component designs. You'll participate in defining architecture and microarchitecture features of the blocks being designed and perform quality checks across various logic design aspects ranging from RTL to timing/power convergence. You will apply various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation.

Working closely with verification teams, you'll review verification plans and implementation to ensure design features are verified correctly, resolving and implementing corrective measures for failing RTL tests. Additionally, you'll follow secure development practices to address security threat models and security objectives within the design, work with IP providers to integrate and validate IPs at the SoC level, and drive quality assurance compliance for smooth IP/SoC handoff.

• Lead evaluation of architectural trade‑offs considering features, performance targets, power constraints, and system limitations
• Define and document micro‑architecture for complex SoC IP blocks; implement RTL in Verilog/System Verilog, integrate at top level, and deliver fully verified, synthesis‑ and timing‑clean designs
• Collaborate closely with verification teams to ensure comprehensive coverage and robust validation of all design aspects
• Develop and maintain timing constraints for IP blocks; provide guidance and support to physical design teams for synthesis, timing closure, and formal equivalence checks
• Drive silicon bring‑up and post‑silicon validation, including debug and performance analysis
• Mentor junior engineers and contribute to best practices for design methodology and quality

• Ability to thrive in a dynamic environment with evolving requirements
• Strong communication skills, collaborative mindset, and leadership qualities
• Passion for innovation, continuous learning, and tackling technical challenges

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
• 7+ years of experience in RTL design and implementation for ASIC/SoC development

• Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure
• Hands‑on experience with SoC system integration and multicore CPU subsystem design
• Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
• Expertise in high‑speed and low‑power design techniques
• Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization
• Familiarity with industry standard EDA tools, including simulators (VCS, Questa, Xcelium), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II)

Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always‑on 5G connectivity, Intel is disrupting industries and solving global challenges.

Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.

All qualified applicants will receive consideration for employment without…