Principal DV Engineer – Hybrid; Memory Controller
Listed on 2026-10-07
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Engineering
Test Engineer, Systems Engineer
Rambus seeks a Senior/Principal Design Verification Engineer to join the Memory Controller IP Verification team in Hillsboro, Oregon. The role involves pre-silicon RTL verification for DDR, HBM and GDDR DRAM controllers, with hybrid onsite flexibility.
Responsibilities include testbench creation, coverage planning, regression testing, and verification environment scripting.
Required:
10+ years HDL verification with System Verilog and DDR experience.
This posting is for the Principal DV Engineer – Hybrid (Memory Controller) role at , based in Hillsboro, OR, United States.
We are seeking a motivated Principal DV Engineer – Hybrid (Memory Controller) to join in Hillsboro, OR, United States.
Consider building your career as a Principal DV Engineer – Hybrid (Memory Controller) at
The Principal DV Engineer – Hybrid (Memory Controller) position in the IT & Technology, Engineering field is open for applications.
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