Post-Silicon Validation, Senior Manager

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You have spent years in the lab, oscilloscope probes in hand, hunting down signal integrity issues that make the difference between a chiplet link that trains and one that does not. Managing people came later, but you never stopped being an engineer first. You know what good characterization data looks like because you have collected it yourself, and you can tell when a measurement setup is lying to you before anyone else in the room notices.

Leading a team means you care as much about building the methodology as hitting the milestone. You think about how to make the next testchip bring up faster than the last one, not just whether it passed. When a customer calls with a silicon issue, you are the person who can triage it in real time, decide whether to send someone on-site, and explain the risk to leadership without sugarcoating it.

You have managed budgets, headcount, and lab equipment purchases. You have hired engineers and coached them through career pivots. You understand that the hardest part of this job is not the technical depth, it is making sure the right work happens at the right time with the right people, even when three programs need the same engineer next week.

At Synopsys, you will own the silicon data behind UCIe IP releases and the customer relationships that depend on it being right.

• Lead and directly manage a team of validation and characterization engineers supporting UCIe-based die-to-die interface IP, including hiring, performance management, goal setting, and career development
• Own the characterization and validation of internal silicon testchips end to end, from characterization plan definition through data collection, correlation to simulation and design intent, datasheet parameter confirmation, and silicon sign-off
• Own the customer silicon bring up and debug mission, including sideband and mainband link training, lane repair and reversal, degraded mode operation, and chiplet interoperability, delivered through remote and sometimes on-site lab engagement
• Oversee operational and functional objectives for the group and allocate personnel resources to meet schedules and goals, balancing internal testchip programs against customer commitments that arrive with little notice
• Exercise responsibility for costs, methods, and staffing, including headcount planning, lab capital equipment investment, and the build versus buy decisions behind validation infrastructure and automation
• Establish the standards and methodologies governing characterization execution, measurement and correlation practice, silicon sign-off criteria, and customer lab engagement
• Own the escalation path for critical silicon issues, ensuring the right technical depth is applied and that program and customer risk is communicated early and accurately

• Own the silicon data behind Synopsys' UCIe die-to-die interface IP release decisions, enabling the multi-die and chiplet-based systems our customers are building
• Deliver operational results that directly affect department targets, including sign-off schedules, silicon respin avoidance, and time-to-market for new IP
• Ensure every testchip yields the characterization data the business needs the first time, rather than discovering gaps after the lab window has closed
• Ensure customer silicon comes up quickly and field issues are resolved before they elevate, protecting both customer launches and Synopsys' technical reputation
• Allocate the people, lab capacity, and equipment investment that determine what the organization is capable of characterizing
• Build a team whose depth and methodology outlast any single program or silicon generation
• Shape how the business approaches characterization of next-generation UCIe data rates, packaging technologies, and chiplet topologies

• Bachelor's degree in Electrical or Computer Engineering with a minimum of 10 years of related experience, or an advanced degree with a minimum of 8 years of related experience
• Demonstrated people management experience in a silicon or hardware engineering…