Clock-Gen IP Verification Engineer; Pre-Silicon

Intel Corporation's Central Engineering Group seeks an IP Design Verification Engineer in Hillsboro, Oregon to verify clock generator IPs (PLL/FLL) through pre-silicon stages. You will develop verification environments, tests, and documentation using System Verilog and UVM.

Collaborate with architects, RTL and analog teams to refine verification approaches across IP generations and lead AMS validation activities, ensuring high-quality, scalable IP designs for Intel's next-generation products.

This role, Clock-Gen IP Verification Engineer (Pre-Silicon) at Intel Corporation, could be your next move.

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.

Learn more about the Clock-Gen IP Verification Engineer (Pre-Silicon) role in the description above.

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