Senior EDA Tools Hardware Engineer

Join Intel's mission to engineer world-changing technology as a Senior EDA Tools Hardware Engineer. We are seeking an experienced EDA CAD / Tool Flow Development Engineer to develop and maintain transistor-level timing characterization flows for custom IPs, embedded memories, SRAMs, register files, and compiler-generated macros across advanced semiconductor technologies.

Job Description:

This role focuses on characterization methodology, CAD infrastructure, automation, and model validation for complex custom macros and memory IPs. The engineer will work closely with custom circuit, memory design, STA, and methodology teams to enable scalable and silicon-accurate timing, power, and noise modeling flows. The ideal candidate has strong expertise in SPICE-based characterization, Liberty model generation, custom macro timing behavior, and large-scale automation using industry-standard tools such as Synopsys Nano Time and Cadence Liberate.

• Develop, test, and analyze engineering design automation tools, flows, and methodologies to improve efficiency and optimize power and performance.
• Collaborate with EDA vendors to define, evaluate, and test next-generation design tools and flows.
• Create and verify unique hardware designs, integrating components into hierarchical systems to support end-to-end EDA tool testing for advanced technology nodes.
• Define and enable methodologies for hardware development related to EDA tools and technology node advancements.
• Support and enhance platforms, databases, scripts, and tools used for design automation.
• Provide digital design, verification, full-chip integration, physical layout, power, performance, clocking, and timing for future TFM development.

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Degree in one of the following options:
  • Option 1:
    Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field, with 6+ years of relevant experience.
  • Option 2:
    Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 4+ years of relevant experience.
  • Option 3:
    Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or in a related field with 2+ years of relevant experience.
• 3+ years of experience with Timing characterization methodologies in one of the following: (i.e. Nanotime, Liberate, or Prime Lib).
• Experience with Liberty timing models.

• Experience in any of the following:
  • SPICE simulation
  • CMOS circuits
  • Memory architecture fundamentals
  • STA fundamentals
  • Advanced-node custom IP or memory characterization flows
  • Scripting and automation skills in Linux environments

Experienced Hire

Shift 1 (United States of America)

US, California, Santa Clara

US, California, Folsom, US, Oregon, Hillsboro, US, Texas, Austin

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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