IP Design Verification Engineer

## IP Design Verification Engineer Apply:
US, Oregon, Hillsboro:
US, California, Folsom:
Full time:
Posted Today:
JR0287351#
** Job Details:**##

Job Description:

** About the Role
** Join our Logic Design and Validation group within the Design Technology Platforms department, where you'll play a key role in shaping the future of semiconductor technology. You'll be part of a dynamic team responsible for developing RTL models and pre-silicon validation tests for test chips on next-generation silicon manufacturing processes. This is an opportunity to work at the cutting edge of chip design, collaborating across multidisciplinary teams to deliver robust, high-quality silicon.

** What You'll Do*
* ** What You'll Do**
* ** Design & Develop Verification Environments** – Build and maintain scalable, reusable UVM-based test benches and test cases for complex mixed-signal CMOS designs at the block, subsystem, and SoC levels.
* ** Define Verification Strategy** – Own and drive comprehensive verification plans for complex digital systems, ensuring thorough coverage closure across multiple projects.
* ** RTL Development & Integration** – Develop RTL designs and integrate logic components into SoC architectures, collaborating with IP providers to validate IPs at the system level.
* ** Power Methodology** – Develop and implement power verification methodologies for complex mixed-signal IPs using industry-standard frameworks.
* ** Assertion-Based Verification** – Create and apply System Verilog Assertions (SVA) to strengthen coverage closure and improve overall verification quality.
* ** Debug & Root Cause Analysis** – Identify, debug, and resolve pre-silicon failures, implementing corrective measures and driving issues to closure.
* ** Cross-Team Collaboration** – Partner with architecture, physical design, and post-silicon teams to continuously improve verification strategies for complex architectural features.
* ** Continuous Improvement** – Incorporate post-silicon learnings and feedback into enhanced pre-silicon verification methodologies.
* ** Documentation & Reviews** – Maintain detailed test plans and lead technical reviews with design and architecture teams.  
** Behavioral Traits
*** Self-motivated with a strong sense of urgency and commitment to delivering results.
* Excellent communication and interpersonal skills with the ability to work effectively across teams.
* Strong analytical and troubleshooting skills with a structured approach to problem-solving.
* Clear and concise documentation and presentation abilities.##
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* Qualifications:

** The Minimum qualifications are required to be initially considered for this position.  Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
** Minimum Qualifications**
* ** Option A:
** Master's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 1+ years of relevant experience.
* ** Option B:
** Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 3+ years of relevant experience.
* Experience with Pre-silicon logic validation using System Verilog and UVM.
* Experience in Digital design using Verilog and/or System Verilog.
* Experience with pre-silicon validation closure across multiple projects.
* Hands-on experience with UVM testbench design, with a focus on reusability and scalability.
* Experience with end-to-end validation strategies for complex digital systems.
* Experience with System Verilog Assertions (SVA) for coverage…