Senior Analog and Mixed Signal Design Engineer

## Senior Analog and Mixed Signal Design Engineer Apply:
US, Oregon, Hillsboro:
US, California, Santa Clara:
Full time:
Posted Today:
JR0288356#
** Job Details:**##

Job Description:

** The Group
** Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) drives pathfinding and development of the analog/mixed-signal and high-speed I/O IP that defines what Intel's leading-edge process technologies can deliver. The High-Speed I/O team develops Ser Des and die-to-die interface reference designs and test chips that co-optimize Intel process technology with next-generation wireline standards, including high-speed PAM4 electrical links, PCIe, UCIe, and HBM.
** The Role
** We are seeking a senior technical expert in high-speed Ser Des circuit design and Ser Des system architecture. You will own Ser Des link architecture on Intel's leading technology test chips, from link budget and equalization strategy down to transistor-level design of the critical analog front-end and clocking blocks. You will also translate link requirements into device, interconnect, and design-rule requirements that shape future Intel process nodes.

This is a senior individual-contributor role with technical leadership across design, layout, and measurement engineers.
** Responsibilities
* ** Define Ser Des link architecture for next-generation interfaces (224G/448G-class PAM4 electrical links, PCIe Gen7/Gen8, UCIe): channel analysis, link budget, jitter and noise budgeting, and equalization partitioning across TX FFE, RX CTLE, DFE, and ADC/DSP-based receivers.
* Build and maintain system-level link models (statistical and time-domain, in MATLAB or Python; COM and IBIS-AMI based) and use them to derive block-level specifications for TX, RX, ADC, and clocking circuits.
* Lead transistor-level design of critical Ser Des blocks: TX drivers (SST/CML) with FFE, RX AFE (CTLE, VGA, termination, T-coil and ESD co-design), DFE and slicers, time-interleaved ADC front ends, CDR and phase interpolators, LC and ring PLLs, and clock distribution.
* Drive test-chip definition, integration, tapeout readiness, and silicon bring-up; correlate measured BER, eye, jitter, and power against models, and lead root-cause analysis of silicon-to-model gaps.
* Translate Ser Des requirements into process and PDK requirements (device fT/fmax and parasitics, BEOL RC, inductor Q, matching, ESD capacitance budget, reliability and aging) and drive design-technology co-optimization with process, PDK, and template-library teams.
* Provide technical leadership: mentor engineers, lead design reviews, and represent Intel Foundry in technical engagements with IP partners and foundry customers.##
*
* Qualifications:

** You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
** Minimum Qualifications
*** Bachelors Degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 6+ years of industry experience in high-speed wireline Ser Des circuit design experience
-OR
- Master's degree in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 4+ years of industry experience in high-speed wireline Ser Des circuit design,
-OR-  Ph.D. in Electrical Engineering, Computer Engineering, or Electrical and Computer Engineering with 2+ years of industry experience in high-speed wireline Ser Des circuit design.
* Experience in Transistor-level design of Ser Des TX, RX, or clocking circuits in at least one silicon-proven design at 28 Gb/s per lane or higher.
* Experience in at least one of the following:  + Ser Des…