Senior AI Systems Architect​/Researcher

## Senior AI Systems Architect/Researcher Apply:
US, Oregon, Hillsboro:
US, California, Folsom:
US, California, Santa Clara:
Full time:
Posted Yesterday:
JR0288178#
** Job Details:**##

Job Description:

##
** About Central Engineering Group — Networking Architecture
** The CEG Networking Architecture Group defines next-generation networking silicon and platform architecture for hyperscale data centers, cloud infrastructure, and AI workloads. The team focuses on IPU/DPU platforms, advanced packet processing, programmable networking, and the data-movement technologies that enable modern distributed computing systems to scale efficiently.##
** Position Overview
** This role is for a senior AI systems architect who can translate the communication, memory, and orchestration bottlenecks of large-scale AI into networking architecture, IP, and platform direction. The successful candidate will work across research, architecture, silicon, software, and product teams to shape the next generation of distributed AI infrastructure.

As a Senior AI Architect/Researcher, you will help define how AI systems communicate and move data at scale across xPUs, DPUs, IPUs, NICs, memory, and heterogeneous storage. In this pathfinding and research role, you will advance new architectural approaches and translate research insights into network architecture and software capabilities that can influence N+1 to N+3 product roadmap.

The ideal candidate thinks in systems rather than components, understands the memory wall and scale-out serving bottlenecks, and can reason across interconnect, memory hierarchy, software runtime, and compute to unlock the next order of magnitude in AI efficiency. You will help set technical direction and influence silicon and software roadmaps. The candidate is expected to maintain substantial knowledge of state-of-the-art principles and theories, contribute regularly to scientific literature and the research community-at-large, and may participate in the development of Intellectual Property.##

** Key Responsibilities
**** Turn Workload Analysis into New IP*
* • Analyze real AI serving and training workloads, identify communication and memory bottlenecks, and translate those findings into new IP, offload engines, platform features, and architecture requirements
• Drive hardware-software co-design across compute, DPU/IPU, NIC, SoC fabric, and AI serving runtimes, ensuring that networking and data-movement capabilities are reflected in modern inference and training frameworks such as vLLM, SGLang, and others
** Architect AI-Scale Networking and Interconnect*
* • Define the architectural direction for how AI systems and infrastructure move data at scale across xPU-to-xPU, xPU-to-storage, and cross-node paths spanning IPU/DPU platforms, NICs, and heterogeneous storage
• Shape next-generation packet processing, RDMA-class transport, and programmable networking IP that forms the backbone of hyperscale AI inference and training
** Attack the Memory Wall and System-Level Bottlenecks*
* • Investigate the fundamental data-movement bottlenecks in large-scale AI and Agentic inference and training, including KV-cache transfer, disaggregated prefill/decode, model and tensor parallelism, and communication collectives, and translate them into concrete architectural requirements
• Reason across the full memory hierarchy and interconnect to minimize copies, latency, and bandwidth overhead, balancing latency-sensitive control paths against bandwidth-intensive data-paths
** Set Roadmap and Lead Across Teams*
* • Shape multi-generation compute, memory, and interconnect roadmaps across IPU/DPU product lines by defining scaling strategies, migration paths, and architecture requirements that connect research insights to product…