SoC Physical Design Implementation Lead

Location: Markham

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE We are seeking a seasoned SoC Physical Design Implementation Lead to own full-chip physical design strategy and execution for AMD’s next-generation Instinct AI and data center processors. This role spans complex SoC architectures with chiplets, 3D stacking, and advanced nodes (3nm/2nm), requiring deep expertise in PPA optimization and sign-off. You will drive methodology innovation, including AI-driven and data-driven automation, while collaborating closely with global SoC teams to deliver industry-leading performance and efficiency  PERSONYou combine deep technical mastery with the ability to influence and collaborate across global teams.

You thrive in complex problem-solving environments and embrace data-driven approaches and emerging technologies. Your communication skills let you clearly articulate design trade-offs and rationale. You are passionate about advancing the craft—whether through internal trainings, technical publications, or presenting at industry conferences—and you bring curiosity, adaptability, and resilience to a fast-paced environment where innovation and execution excellence go hand in hand.

KEY RESPONSIBILITIES Lead SoC-level Physical Design strategy and execution for large, complex chips, including floor planning, placement, CTS, routing, timing sign-off, and tapeout as part of the Instinct Physical Design team.

Drive power optimization, PPA closure, and sign-off for advanced nodes (3nm/2nm) on multi-chip architectures with chiplets and 3D stacking.

Develop and implement advanced physical design methodologies, including AI-driven and data-driven automation, to accelerate design convergence and productivity.

Collaborate with cross-functional SoC, architecture, and verification teams to ensure performance, quality, and schedule goals are met.

Provide technical leadership and mentorship, influencing best practices across physical design teams while continuously improving flows and execution efficiency.

PREFERRED EXPERIENCE Experience with advanced process nodes, including 3D stacking and integration technologies.

Strong, hands-on expertise in place & route (P&R), static timing analysis (STA), clock distribution, physical verification, and chip-level integration.

Proven ability to implement power optimization strategies and achieve PPA closure on large SoCs.Advanced knowledge of CAD tools from Synopsys, Cadence, and Siemens (Mentor Graphics).Practical experience applying AI or ML techniques, AI-assisted tools, or data-driven automation to improve physical design quality and efficiency.

Skilled in scripting languages such as Tcl, Perl, and Shell for automation and productivity.

Demonstrated capability as a self-starter, independently delivering complex, time-critical technical solutions.

ACADEMIC CREDENTIALSBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or equivalent preferred.#LI-LC3#LI-HYBRID Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters,…