Senior Memory Layout Engineer

Location: Vasanthanagar

Senior Memory Layout Engineer

Location:

Bengaluru

Experience:

4–10 Years

Role Overview
We are looking for a  Senior Memory Layout Engineer  with strong hands-on expertise in  memory/custom layout  for advanced technology nodes, including  2nm, 3nm, and 5nm FinFET  processes.

Key Responsibilities
Develop  memory macro and custom layouts  from floorplan through tapeout.
Work on  SRAM bitcell, memory arrays, and peripheral circuit layouts .
Execute layout optimization for  area, density, matching, parasitics, and performance .
Implement advanced-node  FinFET layout techniques and design-rule requirements .
Perform and debug  DRC, LVS, ERC, PEX and physical verification .
Analyze  parasitic effects, EM/IR and layout-dependent effects .
Collaborate with  Memory Design, Circuit Design, Physical Verification and Technology teams .
Support  tapeout, signoff and post-layout correlation .
Core Technical Skills
4–10 years  of Memory / Custom Layout experience.
Strong hands-on experience with  2nm / 3nm / 5nm FinFET  technologies.
Expertise in  SRAM / memory macro layout  and advanced-node design rules.
Strong knowledge of  matching, symmetry, shielding, guard rings and sensitive-net routing .
Proficiency in  Cadence Virtuoso / Custom Layout .

Experience with  Calibre / PVS, DRC, LVS, ERC and PEX .
Strong understanding of  parasitic optimization and layout-dependent effects .
Advanced-node tapeout experience  is highly preferred.
Ideal Profile:  A hands-on memory layout engineer capable of delivering  tapeout-quality SRAM/memory layouts at advanced FinFET nodes , with strong ownership of  area, quality, parasitics and physical verification .