Lead Static Timing Analysis; STA) Engineer

Position: Lead Static Timing Analysis (STA) Engineer
Location: Vasanthanagar

Lead Static Timing Analysis (STA) Engineer

Experience:

6 to 10 years  of experience in STA.
Location :

- Bangalore

Job Summary
The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics.

Key Responsibilities
Timing Sign-off and Analysis
Timing Closure Ownership:
Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip.
Constraint Management:
Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.g., Scan, MBIST).
MMMC Analysis:
Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner).
Critical Path Identification:
Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations.
Signal Integrity (SI) & Noise:
Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process.

Methodology and Flow
Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime.
Automate repetitive tasks and report generation using scripting languages.
Generate final timing reports and sign-off collateral for tape-out.

Education
Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field.

Technical Skills
EDA Tools:  Expert proficiency with industry-standard  Electronic Design Automation (EDA)  tools from vendors like Synopsys (e.g., Fusion Compiler, ICC2, Primetime), Cadence (e.g., Innovus), or Mentor Graphics.