Senior Signal Processor; SIGPRO Engineer

Key Responsibilities:

• Serve as theitechnical lead for the AN/SPY-1 Signal Processor subsystemiacross all radar variants (D, D(V), D(MOD)).
• Lead efforts to analyze and document thei design and functional behavior of legacy signal processor components, including digital processing modules, interface cards, and timing assemblies.
• Supporti design recovery and traceability efforts, working from GFI, limited technical data, or harvested hardware.
• Define and support the development ofi prototype subassemblies, repair processes, and test capabilities to validate organic sustainment approaches.
• Develop and validatei functional test procedures, signal flow diagrams, and performance benchmarks.
• Identifyi critical components at risk due to obsolescence, and support alternate part qualification, reverse engineering, or redesign as necessary.
• Coordinate with systems engineers, test engineers, and OEM partners to ensure alignment withi weapon system interface requirements and mission-critical timing/data processing functionality.
• Provide technical input toi Integrated Technical Data Packages (ITDPs), depot stand-up planning, and operator/maintainer training materials.
• Ensure test and repair processes comply withi NAVSEA and METCAL standards where applicable.

Keyword: SIGPRO, AEGIS

Required Experience:

• Bacheloris degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Minimum of 10+ years of experience with radar or advanced signal processing systems
  , including 5+ years supporting AN/SPY-1 or equivalent phased array radar systems.
• Deep understanding of legacy digital processing architectures
  , A/D conversion, timing synchronization, and signal conditioning.
• Experience with diagnostics, troubleshooting
  , and repair at the board and component level.
• Familiarity with tools used for signal integrity analysis, logic analyzers, and boundary scan testing.
• Proven ability to read, interpret, and reverse-engineer technical data, schematics, and embedded processing logic.
• Experience developing or reviewing test procedures and technical documentation for government sustainment programs.
• Active Secret Clearance

• Prior work with AEGIS Combat System interfaces
  , SPY-1 timing architectures, or radar track processing functions.
• Familiarity with DoD obsolescence mitigation strategies
  , including reverse engineering, emulation, and form-fit-function redesign.
• Experience supporting ORDALT implementation
  , depot activation, or prototype validation.
• Knowledge of Model-Based Systems Engineering (MBSE) practices or digital engineering toolsets.
• Active TS/SCI Clearance

~10i 20%, including to shipyards, government labs, and partner facilities.

(No phone calls please)