Principal Analog Design Engineer Speed Interconnects
Job in
Irvine, Orange County, California, 92713, USA
Listed on 2025-12-22
Listing for:
Celero Communications
Full Time
position Listed on 2025-12-22
Job specializations:
-
Engineering
Electronics Engineer, Systems Engineer, Electrical Engineering, Hardware Engineer
Job Description & How to Apply Below
Principal Analog Design Engineer
About the Role:
Are you a seasoned Analog Design Engineer ready to lead the development of disruptive high-speed interconnect technology for next-generation AI systems? Join a fast‑growing startup building an elite team of diverse engineers focused on high‑speed mixed‑signal circuit designs. We are looking for a Principal Analog Design Engineer who is motivated by innovation and technical leadership, and excited to design high‑performance analog circuitry powering advanced transceivers.
- Design high‑speed analog circuits such as broadband amplifiers, drivers (DRV), and transimpedance amplifiers (TIAs).
- Develop critical analog blocks including TIA, VGA, CTLE, Pre-DRV, DRV, etc.
- Innovate and implement new techniques for next‑generation optical transceivers.
- Perform custom passive component design from concept through silicon implementation.
- Supervise analog layout efforts using advanced process nodes (e.g., FinFET).
- Create system‑level verification plans and detailed circuit design specifications.
- Lead silicon bring‑up, debugging, and validation efforts.
- Effectively communicate and document designs within cross‑functional teams.
- Master’s degree and/or Ph.D. (preferred) in Electrical Engineering or related fields.
- 5+ years of experience in high‑speed analog design.
- Strong analog design fundamentals with experience in broadband amplifiers, VGA, CTLE, TIA, DRV (>50GHz Bandwidth).
- Proficient with analog design and verification tools (Virtuoso, Spectre, ADE, post‑layout extraction tools).
- Experienced with electromagnetic simulation tools (EMX, Momentum, HFSS, or equivalent).
- Strong understanding of electromagnetism, lumped models, and high‑frequency design principles.
- Experience with system‑level pre‑tape‑out analog validation.
- Understanding of analog layout design in FinFET processes and its impact on performance.
- Experience in lab chip bring‑up and debugging is a plus.
- Excellent communication and documentation skills.
Location:
Irvine, CA
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