Sr. SOC/ASIC Physical Design Engineer; Silicon Engineering
Listed on 2026-01-04
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Engineering
Systems Engineer, Electrical Engineering
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) role at SpaceX
. 3 days ago – be among the first 25 applicants.
Space
X was founded under the belief that a future where humanity explores the stars is fundamentally more exciting than one where we are not. Today, Space
X actively develops technologies to make this possible, including Starlink, the world’s largest satellite constellation providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers, and the software that ties it together. We are looking for best‑in‑class engineers to help maximize Starlink’s utility.
We seek a motivated, proactive, and intellectually curious engineer who will work with cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role you will develop cutting‑edge silicon for deployment in space and ground infrastructures, enabling connectivity where it has previously been unavailable, unaffordable, or unreliable.
Responsibilities- Perform partition synthesis and physical implementation steps (synthesis, floor planning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency, and other sign‑off checks).
- Develop or improve physical design methodologies and automation scripts for various implementation steps.
- Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design trade‑offs.
- Resolve design, timing, congestion, and flow issues, identify potential solutions, and drive execution.
- Run, debug, and fix sign‑off closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop.
- Bachelor’s degree in electrical engineering, computer engineering or computer science.
- 5+ years of ASIC and/or physical design flow development experience in industry.
- Strong experience in ASIC/SOC RTL2
GDSII physical design and sign‑off flows. - Strong experience with industry‑standard EDA tools and understanding of their capabilities and underlying algorithms.
- Knowledge of deep sub‑micron FinFET and CMOS solid‑state physics.
- Knowledge of CMOS digital design principles, basic standard cells and their functionality, standard cell libraries.
- Understanding of CMOS power dissipation in deep sub‑micron processes include leakage/dynamic.
- Familiarity with CMOS analog circuit and physical design.
- Knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows.
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile, etc.).
- Self‑driven individual with a can‑do attitude, willing to learn, and able to work in a dynamic group environment.
- Must be willing to work extended hours and weekends as needed.
Pay range:
Physical Design Engineer/Senior: $ – $ per year. Salary determined on case‑by‑case basis based on job‑related knowledge, experience, and education.
Base salary is one part of your total rewards package. Eligible for long‑term incentives such as company stock, stock options, long‑term cash awards, discretionary bonuses, and the Employee Stock Purchase Plan. Benefits include comprehensive medical, vision, and dental coverage; 401(k) retirement plan; short and long‑term disability insurance; life insurance; paid parental leave; discounts and perks. Eligible for 3 weeks paid vacation and 10 or more paid holidays per year.
Exempt employees eligible for 5 days sick leave per year.
- U.S. citizenship or national, U.S. lawful permanent resident (green card holder), refugee under 8 U.S.C.1157, or asylee under 8 U.S.C.1158.
- Or be eligible to obtain the required authorizations from the U.S. Department of State.
- Learn more about the ITAR requirements.
Space
X is an Equal Opportunity Employer; employment with Space
X is governed on the basis of merit, competence, and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of Space
X’s affirmative action plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process, may reach out to
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