Power Management IC Design Lead

What you will be doing

• Responsible for the design/lead of the Power Management IC deliverable for LTE, GNSS, WiFi, Bluetooth, Zigbee, and other communication systems.
• The ideal candidate can design Analog/Power Management building blocks as well as PMU Top-Level (layout, digital, RFIC and system).

Experience you will need:

• MS or Ph.D. in Electrical Engineering with 10+ years of experience in Analog/PMU design with advanced CMOS technology nodes.
• SOI technology experience is a plus.
• Experience as Design Lead for Power Management IC. Open to candidates with extensive experience designing PMU building blocks with Design Lead aspiration/capability.
• Detailed knowledge with direct tape-out experience in several of the following a MUST: LDO, Bandgap, DC-DC Converter, various ADC/DAC architectures, OPAMP/Amplifiers, Comparators, Analog Filters, Variable Gain Amplifiers, XTAL Oscillators, Ring Oscillator, etc. Emphasis on LOW POWER DESIGN.
• Good understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, offset and other analog impairments.
• Knowledge of QFN & CSP packaging effects, supply isolations, circuit layout for optimum Analog/RF performance, EM effects, PEX (post-layout parasitic extraction).
• Experience in using development tools including Cadence Virtuoso, Spectre RF, MATLAB, and Verilog modeling.
• Understanding of system specifications and ability to translate system requirements into circuit requirements at IC level.
• Hands-on experience in silicon characterization and debugging.
• Team player with good verbal and written communication skills along with excellent presentations skills (MS Office Suite). Strong sense of urgency.

Desired Qualifications

• 12+ years of Analog/PMU Design.
• Technical Lead experience is a plus.
• Experience with Power Management IC top-level simulation & verification.