Sr​/Principal Layout Engineer

We are seeking an experienced Analog / RFIC Layout Engineer to join our fast-growing design team. In this role, you will partner closely with our analog and RFIC design engineers to bring complex, high-frequency circuit designs to life. You will lead the layout phase from floor planning to tape-out, playing a critical role in developing our next-generation, ultra-low power SoC interconnect solutions.

Responsibilities:

• Collaborate closely with Analog/RFIC designers to perform custom block-level and top-level layouts.
• Own the physical implementation
  , including full-chip integration, floor planning, and complex routing for sensitive RF and analog macros.
• Execute physical verification by running, analyzing, and independently debugging DRC, LVS, ERC, and Antenna checks.
• Optimize for performance using advanced high-frequency layout techniques (precise device matching, shielding, isolation, and minimizing parasitic extraction).
• Ensure reliability by analyzing and resolving Electromigration (EM) and IR drop issues.
• Streamline processes by developing methodologies to simplify custom macro integration into top-level Place & Route (P&R) flows.
• Drive tape-out success by supporting tight deadlines and working dynamically across multiple advanced-node projects.

Qualifications:

• Education: B.S. in Electrical Engineering, or a college diploma in Electrical Engineering, Electronics Technology, or a related technical field, combined with a certificate from a recognized IC Layout training program.
• Experience: Proven track record 10+ years in custom analog, mixed-signal, and RF layout design in mm wave frequencies (>20GHz).
• Tool Mastery: Deep proficiency with industry-standard layout and verification platforms (e.g., Cadence Virtuoso, Siemens Calibre, StarRC/Quantus).
• RF Layout Expertise: Thorough understanding of RF layout fundamentals, including signal integrity, symmetry, multi-path matching, and guard rings.
• Advanced Nodes: Hands-on experience with HBT processes such as SiGe, GaAs etc.
• Problem Solver: Strong ability to identify schematic or layout bottlenecks and work seamlessly with circuit engineers to resolve layout-induced design challenges.
• Team Player: Excellent communication skills with a collaborative, startup-ready mindset.

Preferred Qualifications:

• Experience with high-speed serial links (e.g., 56G/112G PAM4, Ser Des) or mmWave RFIC layout in >60GHz.
• Automation and scripting skills (SKILL, Python, TCL, or Perl) to enhance layout efficiency.
• Understanding of LEF creation and debugging to support P&R teams.

Location(s)

• Irvine, CA (Orange County area)

The base pay range for this role is $170,000 – $258,000 annually. Base pay will be determined by skills, qualifications, experience, and location.