Senior -Speed Analog Layout Lead IP Blocks
Listed on 2026-11-04
-
Engineering
Electronics Engineer, Hardware Engineer
Celero Communications is a fast-growing semiconductor startup seeking a High-Speed Analog Layout Design Engineer to lead the physical layout of ADCs, DACs, PLLs and other high-performance analog/mixed-signal circuits.
You will interface with circuit designers, CAD/PDK teams, and layout engineers across time zones, mentoring junior staff and ensuring first-pass silicon success in a fast-paced environment.
The following opportunity is for a Senior High-Speed Analog Layout Lead for IP Blocks with Celero Communications.
Step into the Senior High-Speed Analog Layout Lead for IP Blocks role at Celero Communications in Irvine, CA, United States and grow with us.
Please review the full job details above before applying.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in Irvine, CA, United States.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).