Senior DFT Engineer: ASIC/SoC Test & Yield
Listed on 2026-11-04
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Engineering
Test Engineer, Quality Engineering, Electronics Engineer
Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. You will partner with design, verification, physical design, product, and manufacturing teams to implement robust DFT methodologies that enable high quality, high volume production of complex ASIC and SoC products.
As a DFT Engineer, you will develop and implement DFT architecture for ASIC/SoC designs, perform scan insertion, planning, and compression, generate ATPG patterns, and verify MBIST
As a Senior DFT Engineer: ASIC/SoC Test & Yield, you will play an important part at Celero Communications in Irvine, CA, United States.
The following opening is for a Senior DFT Engineer: ASIC/SoC Test & Yield with Celero Communications.
Our team is growing, and we are hiring a Senior DFT Engineer: ASIC/SoC Test & Yield in Irvine, CA, United States.
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