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Senior Lead DSP/RTL Design Engineer; FPGA/ASIC)
Job in
Irvine, Orange County, California, 92713, USA
Listed on 2026-11-04
Listing for:
Infineon Technologies
Full Time
position Listed on 2026-11-04
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
A leading semiconductor firm in Irvine, CA is seeking a Lead Principal Engineer for Digital Design. This role involves implementing DSP algorithms in Verilog/System Verilog and collaborating with teams on hardware architecture. Candidates should have 15+ years of RTL design experience and strong knowledge of fixed-point math and DSP fundamentals. This position offers a competitive salary range between $201,400 and $277,000, plus participation in an incentive plan.
We are currently recruiting a Senior Lead DSP/RTL Design Engineer (FPGA/ASIC) for our team in Irvine, CA, United States. The advertised compensation is 201.. We aim to respond to suitable candidates as soon as possible. Full responsibilities and requirements are described in the listing above. Learn more about the Senior Lead DSP/RTL Design Engineer (FPGA/ASIC) role in the description above.
Position Requirements
10+ Years
work experience
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