Senior Analog/Mixed-Signal Verilog Modeling Engineer
Listed on 2026-11-05
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Engineering
Electronics Engineer, Test Engineer
Broadcom Inc. in Irvine seeks an experienced DMS model developer to create Digital‑Mixed Signal models for analog IPs using System Verilog. You will interface with analog design and DV teams to support verification, and leverage Verilog‑AMS for modeling and Cadence tools for linting and simulation.
The role requires a strong background in RTL/DTL coding, testbench creation, and hands‑on scripting (TCL/Perl/Python) with exposure to AI-assisted modeling approaches.
The Senior Analog/Mixed-Signal Verilog Modeling Engineer role at Broadcom Inc. is now open for applications in Irvine, CA, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior Analog/Mixed-Signal Verilog Modeling Engineer role in the description above.
We appreciate your interest in this position.
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