Senior -Speed Analog Layout Engineer — Cut-Edge IP

Celero Communications, Inc. is seeking a High-Speed Analog Layout Design Engineer to drive layout of ADCs, DACs, PLLs and other high-performance blocks for optical communication systems.

You will lead the AMS layout team, mentor engineers across time zones, and collaborate with circuit designers to ensure first-pass silicon success. The role requires extensive hands-on experience in analog/mixed-signal layouts,Cadence Virtuoso and Calibre, and familiarity with top-level integration and

The Senior High-Speed Analog Layout Engineer — Cut-Edge IP role at Celero Communications, Inc. is now open for applications in Irvine, CA, United States.

This is a strong role to take on the Senior High-Speed Analog Layout Engineer — Cut-Edge IP role at Celero Communications, Inc.

As a Senior High-Speed Analog Layout Engineer — Cut-Edge IP, you will play an important part at Celero Communications, Inc. in Irvine, CA, United States.