Senior Principal​/Distinguished Engineer – SerDes Analog​/Mixed-Signal Design

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical.

Our team is talent-dense andhigh-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard.

About the Role

Upscale AI is developing next-generation Ser Des technology to enable the bandwidth, power efficiency, and scalability required by future AI infrastructure. We are seeking exceptional analog and mixed-signal design engineers to drive the development of complex, high-performance circuits and help shape the technical direction of our Ser Des platform.

As a Senior Principal / Distinguished Engineer, you will lead technically challenging design efforts, influence circuit and subsystem architecture, and drive critical design decisions across multiple engineering disciplines. You will bring deep circuit expertise, strong engineering judgment, and a system-level perspective to deliver differentiated high-speed silicon solutions.

Responsibilities

• Lead the design and implementation of complex high-speed analog/mixed-signal circuits and critical Ser Des IP.
• Define circuit approaches and design methodologies to achieve aggressive performance, power, area, and robustness objectives for 100G+ Ser Des PHYs.
• Resolve the most challenging circuit-design issues through first-principles analysis, modeling, simulation, and silicon-based investigation.
• Lead technical reviews and influence decisions across architecture, analog/mixed-signal design, digital design, layout, physical design, and validation.
• Drive design closure across complex implementations, including post-layout verification, performance optimization, and silicon correlation.
• Identify opportunities for architectural innovation, design automation, and improved engineering efficiency.
• Contribute to technical roadmaps, project planning, and risk mitigation for next-generation Ser Des products.
• Promote rigorous engineering practices, design quality, and knowledge sharing across the organization.

Qualifications:

• M.S. or Ph.D. in Electrical Engineering or a related field.
• Extensive experience in analog/mixed-signal IC design, 100G+ high-speed circuit design, or advanced semiconductor product development.
• Demonstrated record of successfully delivering complex circuit designs from architecture through implementation and silicon validation.
• Strong debugging skills and the ability to solve ambiguous, cross-disciplinary technical problems.
• Excellent technical communication skills and the ability to influence engineering decisions across teams.

Preferred Qualifications:

• Significant experience developing 100G+ high-speed Ser Des or other high-performance analog/mixed-signal IP.
• Expertise in advanced CMOS process technologies and the associated challenges in circuit design, physical implementation, and variability.
• Proven expertise in one or more of the following technical areas:
• Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider (MMD).
• Phase interpolator, injection-locked oscillator, multi-phase clock generator.
• High-speed time-interleaved DAC and line driver.
• Transimpedance amplifier, CTLE, PGA, Cherry-Hooper amplifier, high-speed voltage followers.
• Time-interlea…