Senior Firmware Engineer

Job Title:

DDR5 Firmware Initialization and Margining Engineer - Senior to Staff Level

Montage Technologies is opening a new U.S. location in the Johns Creek, GA area offering a Hybrid work environment. We are an emerging semiconductor company specializing in enterprise class memory products. There will be many hands-on learning experiences with significant program ownership and career growth.

Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. Montage Technology provides industry leading DDR2 to DDR5 memory interface products for the demanding cloud computing and data center markets. Our robust product portfolio includes the critical components required by the memory modules, such as Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM with Hub (SPD Hub), Temperature Sensor (TS) and Power Management IC (PMIC).

Compliant with JEDEC specifications, these products are designed for a variety of memory modules such as RDIMM, LRDIMM, NVDIMM, UDIMM, SODIMM, MRDIMM, etc., to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing. Montage is quickly growing to become the leader in these industries, with revenue having grown 171% in the last 5 years!

The Role:

We are seeking a Senior Software/Firmware Engineer to develop, debug, and optimize the DDR firmware for memory initialization, training, and margining that brings up and configures memory subsystems across our silicon platforms. This is a hands-on role focused on implementing training and margining algorithms, memory initialization sequences, and low-level firmware that enables reliable, high-performance memory operation from first power-on through production.

You will collaborate with partner firmware teams, silicon design, memory subsystem architecture, and lab validation teams throughout the development lifecycle — from pre-silicon RTL simulation through post-silicon bring-up and characterization.

• Key Responsibilities:
• Develop, debug, and maintain embedded firmware and low-level software for memory training, initialization, and margining (e.g., DDR5 PHY training, receive-enable, read DqDqs training, MBIST/RMT, eye/timing-voltage margining, DRAM controller initialization).
• Implement and optimize memory training and margining algorithms in collaboration with hardware designers and memory subsystem architects.
• Develop and run margining sweeps and eye-margin analysis to characterize and optimize DDR timing/voltage margins across process, voltage, and temperature (PVT).
• Work with signal integrity and equalization techniques — including CTLE, DFE, and related receiver equalization/training — to tune link margins and optimize high-speed DDR signal quality.
• Support memory initialization, configuration, training, and runtime management across the platform lifecycle.
• Debug hardware/firmware interactions during bring-up and post-silicon validation.
• Define and execute firmware-hardware co-validation plans together with the validation team.
• Develop scripts and tools to automate lab equipment, training sweeps, margin sweeps, and data analysis.
• Drive bench validation, characterization, and correlation of training and margining results against specifications.
• Create and maintain firmware design documentation, training/margining algorithm descriptions, and implementation notes.

• Required Skills & Experience
• Please do not apply unless you have a minimum of 5 years of relevant experience.
• B.S. or M.S. in Electrical Engineering, Computer Engineering, or Computer Science.
• 5-15 years of relevant experience in embedded firmware,…