Yield Optimization & Defect Reduction Engineer
Listed on 2026-11-05
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Engineering
Manufacturing Engineer, Process Engineer, Quality Engineering, Electronics Engineer
TSMC Washington is hiring a Yield Enhancement Defect Engineer to identify and eradicate defect sources in high-volume CMOS manufacturing. You’ll apply data analytics, metrology, and cross-functional collaboration to prevent excursions and optimize yields.
The role requires strong analysis, problem-solving, and teamwork skills, with on-site work at the Camas, WA campus. Eligible for sign-on, relocation, and tuition assistance benefits.
We have an opening for a Yield Optimization & Defect Reduction Engineer in WA, United States within Engineering.
The Yield Optimization & Defect Reduction Engineer role at TSMC
- Taiwan Semiconductor Manufacturing Company Limited is now open for applications in WA, United States.
Join us at TSMC
- Taiwan Semiconductor Manufacturing Company Limited as our next Yield Optimization & Defect Reduction Engineer in WA, United States.
We are currently recruiting a Yield Optimization & Defect Reduction Engineer for our team in WA, United States.
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