Digital Verification Engineer

# Digital Verification EngineerA bug that escapes verification on a superconducting chip costs a tape-out, not a patch. You will own the UVM environment, coverage model, and regression infrastructure that prove the RTL does what the microarchitecture says — and nothing it does not.

Team Design Verification Employment Full -time

Posted

May 2026

Role IDSC-Apply Scroll to apply
01

About the Role Snowcap's chip program runs the standard sequence — architecture, microarchitecture, RTL, verification, layout, sign-off — but verification carries an unusual weight here. The logic family is new, the spec is being written for the first time, and the cost of letting a functional bug through to silicon is measured in months and tape-out dollars, not patches. This role is the quality gate between RTL and implementation.  

You will develop and execute the UVM environment for block-level and full-chip verification, define and close functional coverage, write the directed and constrained-random tests, and own the regression infrastructure that runs every night. You will work directly with the Digital Architect, Microarchitect, and RTL design engineers in a flat, matrixed organization. You will also be the engineer who shows up with the evidence — coverage reports, failing seeds, waveforms — that says yes this is real, or no this is testbench, before anyone changes RTL.  

In twelve months, the verification environment you build should be the thing the chip team trusts before tape-out — coverage closed, regressions green for the right reasons, and bugs caught at the level they were introduced. The standards you set for what "verified" means at Snowcap become the standards every future verification engineer inherits.
02

What You'll Own
- Own UVM testbench development for RTL blocks and the full-chip netlist — drivers, monitors, scoreboards, and the reference models the checks rely on.  - Define functional coverage goals against the microarchitecture spec, track them, and close the holes — including the ones that exist only because PCL logic behaves differently than CMOS.  - Write directed and constrained-random tests that exercise SFQ-specific logic behaviors and the corner cases a CMOS-only testbench would never generate.  

- Build and own the chip-level simulation environment and the regression infrastructure that runs it — nightly, on every RTL change, and against the right coverage closure criteria.  - Drive debug cycles with RTL engineers: find root cause, not just symptom, and produce the artifact (waveform, log, test) that makes the bug fixable.  - File, track, and triage functional bugs through to closure — and push back when an "RTL fix" is actually a spec problem the microarchitect needs to resolve.  

- Apply formal verification where it earns its keep — properties, equivalence, model checking on the blocks where directed and random will not get there alone.  - Set the verification methodology and infrastructure standards at Snowcap — testbench architecture, coverage discipline, regression hygiene, and what "signed off for tape-out" actually means.
03

What We Need to See
- Strong UVM and System Verilog verification methodology experience on production silicon that taped out and ran. Hobby and academic verification do not meet this bar.  - Track record of coverage-driven verification — defining the coverage model, closing it, and being able to argue defensibly that what was closed is the right thing to have closed.  

- Working experience with formal verification tools and methodology — properties, assertions, and the judgment to know when to reach for formal instead of throwing more random at the problem.  - Solid working knowledge of the full chip design flow — RTL, synthesis, STA, and the back-end — and…