Design Engineer RF Heterogeneous Integration

Research & Development - Kissimmee, Florida, USA

Help develop next-generation RF heterogeneous integration technologies for applications ranging from AI data centers to space-based communications.

imec USA’s Florida-based R&D Center is developing innovative packaging solutions for next-generation RF (>100 GHz) and ultra-high-speed (>100 Gbps) systems. Applications for these technologies range from AI data centers to space-based communications.

A key area of innovation is the heterogeneous integration of silicon and III-V chiplets on a common interconnect platform. In this role, you will develop building blocks and prototypes that advance imec’s RF interposer technologies, balancing demanding high-frequency performance requirements with manufacturability across a variety of use cases.

As a Design Engineer, you will contribute to the co-design, simulation, and characterization of advanced CMOS and III-V devices heterogeneously integrated on silicon interposers with low-dielectric-loss redistribution layers.

You will work as part of a multidisciplinary, cross-site development team spanning Kissimmee, Florida, and Leuven, Belgium. You will also collaborate closely with external customers and partners on test vehicles and prototypes that help advance cutting-edge RF heterogeneous integration technologies toward real-world applications.

We foster a collaborative, hands-on environment where initiative, technical curiosity, and innovation are encouraged.

• Design circuits and layouts for RF building blocks such as phase shifters, frequency multipliers, power amplifiers, and phase-locked loops that benefit from heterogeneous integration.
• Use electromagnetic simulation to extract parasitic effects and apply those insights to RF interposer-chiplet co-design.
• Design and tape out advanced CMOS circuits using Cadence Virtuoso and associated tools.
• Design and tape out III-V circuits using RF circuit design tools such as Keysight ADS together with electromagnetic simulation tools such as Ansys HFSS.
• Co-design interconnect structures between active chiplets and RF interposers.
• Evaluate tradeoffs between RF performance, signal integrity, packaging, and manufacturability.
• Participate in design reviews and create clear technical documentation, analyses, and reports.
• Collaborate with imec teams in the United States and Belgium as well as external customers and technology partners.
• Contribute to technical publications for international journals and conferences.

• You hold a PhD or a Master’s degree with at least 3 years of relevant professional experience in electrical engineering, microelectronics, RF engineering, or a related technical field.
• You are proficient in Cadence Virtuoso and associated tools used for CMOS chiplet design and tapeout.
• You have experience using Keysight ADS and Ansys HFSS or comparable RF and electromagnetic simulation tools.
• You have a strong understanding of state-of-the-art high-frequency (>100 GHz) and/or high-speed (>100 Gbps) chiplet and integrated-circuit design.
• You have strong written and verbal communication skills and can collaborate effectively with internal teams, customers, and external partners.
• You have very good written and spoken English-language skills.
• You are self-driven, hands-on, pragmatic, and comfortable taking initiative in a multidisciplinary R&D environment.
• Experience with heterogeneous integration is desirable.
• Demonstrated experience taking a chip from tapeout through RF measurement and characterization is highly desirable.
• Experience with semiconductor interconnect and packaging processes such as wafer bumping and flip-chip bonding is desirable.
• U.S. person status is preferred.