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FPGA Engineer – SDR Development

Job in La Mirada, Los Angeles County, California, 90637, USA
Listing for: Argotec INC
Full Time position
Listed on 2026-10-16
Job specializations:
  • Engineering
    Electronics Engineer, Hardware Engineer, Systems Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 120000 - 170000 USD Yearly USD 120000.00 170000.00 YEAR
Job Description & How to Apply Below
Duties & Responsibilities

Your FPGA designs will directly enable high-throughput waveform processing, multi-channel SDR operations, and real-time RF performance in the harsh radiation and thermal environment of space. In this role in our California team, you will report to the Principal Embedded Systems Engineer. You will work closely with system, RF, hardware, and software engineers in a multidisciplinary environment to implement, integrate, and verify high-performance FPGA designs that support signal processing, data handling, and hardware interfaces for space SDR and telecom systems.

  • Develop, implement, and maintain FPGA designs using Verilog, System Verilog, or VHDL for space SDR and telecom systems
  • Design and integrate digital signal processing (DSP) functions such as filtering, modulation/demodulation, channelization, and rate conversion
  • Implement high-speed digital interfaces (e.g., JESD
    204, LVDS, SPI, I2C, Ethernet, Space Wire, or similar) and ensure reliable data transfer between FPGA and peripheral devices
  • Perform simulation, verification, and documentation of FPGA designs using tools such as Questa Sim, and Vivado Simulator (including testbench development and verification plans and artifacts)
  • Support synthesis, place-and-route, timing closure, constraint development, and static timing analysis
  • Integrate FPGA designs with embedded processors, firmware, and software; collaborate across multidisciplinary teams to deliver end-to-end system functionality
  • Support hardware bring-up, lab validation, debugging, and system-level testing (including RF performance and environmental qualification)
  • Analyze and optimize FPGA resource utilization, latency, throughput, and power consumption to meet system requirements
  • Operate laboratory instrumentation (e.g., oscilloscopes, logic analyzers, spectrum analyzers) to support validation and debugging activities
  • Develop and maintain design documentation, including requirements traceability matrices, interface control documents, and verification artifacts
  • Prepare and present FPGA design details at engineering design reviews (e.g., PDR, CDR)
  • Execute assigned tasks independently while coordinating priorities with technical leadership and project schedules
  • Support next-generation processor selections and FPGA architecture updates
General Requirements
  • Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or related fields
  • At least 5+ years of experience in FPGA design and development in a professional or research environment
  • U.S. Citizenship or U.S. Permanent Residency is required
  • Excellent written and oral communication in English

To conform to U.S. Government international trade regulations, the applicant must be a U.S. Citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State or U.S. Department of Commerce.

Required Experience & Skills
  • Team player and a “Do what it takes” attitude
  • Proficiency in Verilog, System Verilog, or VHDL and experience with FPGA tool chains (e.g., Xilinx Vivado) including synthesis, implementation, and timing closure
  • Experience with high-speed digital interfaces (e.g., JESD
    204, LVDS, Ethernet, Space Wire, or similar)
  • Experience designing and implementing digital signal processing (DSP) algorithms in FPGA or fixed-point implementations
  • Understanding of fixed-point arithmetic and numerical effects in FPGA implementations
  • Experience with FPGA verification and validation, including simulation, testbench development, and lab bring-up/debug
  • Strong understanding of digital design fundamentals, including clock domain crossing, reset strategies, IP integration, and HW/SW interfacing
  • Ability to read and…
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