Senior DFT Engineer ASIC​/SoC Test – Onsite

Benefits:

• Day-1 Onsite
• Competitive salary
• Opportunity for advancement

DFT Engineer (Design for Test)

Location:
Santa Clara, CA (Onsite)

Employment Type:
Long-Term Contract

Interview Process:
Virtual Interviews

Compensation:
Based on Experience (DOE)

Engagement: ANY

Preference:
Local candidates or those able to work onsite.

We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team.

In this role, you will be responsible for designing and implementing Design-for-Test (DFT) solutions that ensure high manufacturing quality, test coverage, and efficient production testing for complex semiconductor devices.

Key Responsibilities

• Design and implement DFT architecture for ASIC and SoC designs.
• Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.
• Perform ATPG, fault simulation, and test coverage analysis.
• Support silicon bring-up, debug, characterization, and production test activities.
• Collaborate closely with Design, Verification, Physical Design, and Product Engineering teams throughout the development lifecycle.

Required Qualifications

5+ years of hands-on experience in Design for Test (DFT).

• Strong expertise in Scan, Scan Compression, MBIST, LBIST, ATPG, and JTAG technologies.
• Solid understanding of IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG) standards.
• Experience with one or more industry-standard DFT tools:
  • Synopsys TestMAX / DFT Compiler
  • Siemens Tessent
  • Cadence Modus
• Proficiency in Verilog and/or System Verilog.
• Scripting experience using Python, Perl, Tcl, or Shell.
• Preferred Qualifications
• Experience with ASIC/SoC development.
• Background in silicon bring-up, debug, and production test.
• Strong problem-solving skills and the ability to work effectively in cross-functional engineering teams.

If you’re passionate about developing robust DFT solutions for advanced semiconductor products, we’d love to hear from you.