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Digital Verification Engineer

Job in 1001, Lausanne, Canton de Vaud, Switzerland
Listing for: European Tech Recruit
Full Time position
Listed on 2025-12-07
Job specializations:
  • Engineering
    Electronics Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 CHF Yearly CHF 80000.00 100000.00 YEAR
Job Description & How to Apply Below

Director | Semiconductor, Automotive Tech & Embedded Systems

Digital Verification Engineer – Advanced ASIC/FPGA Systems (Multiple EU Locations)

Locations: Switzerland, UK, Germany or Denmark

About the Role

We are looking for an experienced Digital Verification Engineer to play a key role in validating complex digital designs for next‑generation semiconductor products. This position is ideal for someone who thrives in technical environments, enjoys solving challenging verification problems, and wants to work in a collaborative, high‑performance engineering team.

Key Responsibilities
  • Develop design verification methodologies, standard debug flows, and best‑practice processes.
  • Collaborate closely with RTL designers for verification and validation of digital circuit designs.
  • Participate in design reviews and contribute to architectural and implementation discussions.
  • Build comprehensive verification plans based on specifications and functional requirements.
  • Plan, track, and execute assigned verification tasks to ensure on‑schedule delivery.
  • Use modern simulation tools, verification frameworks, and advanced debugging techniques.
  • Maintain verification environments, monitor regressions, and drive bug tracking and closure.
Skills & Technical Expertise
  • Strong communication skills, analytical mindset, and ability to work effectively in cross‑functional teams.
  • Proficiency in scripting (Python, Perl, Tcl, etc.) and regression management.
  • Deep understanding of simulation‑based verification environments and digital logic design.
  • Strong knowledge of metrics‑driven verification, including test planning, coverage analysis, and closure.
  • Hands‑on experience with simulation tools and modern debug practices.
  • Experience with testbench development using state‑of‑the‑art verification methodologies (e.g., UVM).
  • Experience working with third‑party VIP for protocol or interface verification (advantageous).
  • Understanding of Assertion Based Verification (ABV) and property‑driven methodologies (beneficial).
Experience
  • 5+ years of experience in the semiconductor industry (ASIC or FPGA verification).
  • Proven track record verifying complex, high‑performance digital designs for production applications.
  • Ability to balance quality and schedule constraints effectively.
  • Background in constrained‑random testbench development and functional coverage.
  • Familiarity with high‑speed interfaces or complex protocols (e.g., PCIe, USB, Display Port) is a plus.
  • Strong digital verification foundation with hands‑on experience in UVM‑based verification.
Education

Bachelor’s degree (or higher) in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Research and Engineering

Industries

Semiconductor Manufacturing, Computer Hardware Manufacturing, and Computers and Electronics Manufacturing

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