Mixed Signal Verification Engineer - SerDes​/Speed

We are partnered with a specialist semiconductor company delivering complex high-speed signaling and interconnect solutions. They are seeking a skilled Digital Verification Engineer to contribute directly to the verification and validation of complex ASIC/FPGA circuit designs for high-volume applications.

This is a permanent position based in Lausanne, Switzerland (it is also possible to work from offices in the UK, Germany, or Denmark).

• Develop and implement design verification methodologies and standard debug flows.
• Collaborate closely with designers on the verification and validation of circuit designs.
• Prepare design verification plans and ensure timely completion of assigned verification projects.
• Utilize the latest techniques, tools, and technologies for all verification activities.
• Maintain the verification environment and efficiently track and close design bugs.
• Participate in design reviews and ensure quality through structured verification processes.

• Proven track record in verifying complex ASIC or FPGA designs (preferably in high-volume applications).
• Extensive digital verification background with some UVM (Universal Verification Methodology) experience.
• Experience in constrained random test bench development.
• Strong knowledge of Metrics-Driven Verification (test planning and coverage closure).
• Deep understanding of simulation tools and debugging techniques.
• Proficiency in scripting techniques for regression setup and management.
• Familiarity with Ser Des and high-level protocols (e.g., PCIe, USB, DP) is advantageous.

If you are interested in this Digital Verification Engineer position, please send a copy of your CV to

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