Characterization Lead

Characterization Lead

we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption

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Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

our architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

Join Us at Kandou AI

Lausanne, Switzerland | Up to 30% travel, including Taiwan

Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too.

If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.

As Characterization Lead, you will own performance characterization of Zinal retimer silicon and the Randa Active Electrical Cable (AEC) channel. This is a Principal / Senior Staff individual contributor role with hands-on technical leadership. Your measurements will establish datasheet limits, channel classes and guard-bands for validation, manufacturing and customer specifications. Based primarily in Lausanne, you will work with silicon, signal integrity and validation teams, including channel characterization partners in Taiwan.

• Lead silicon and channel characterization from measurement planning and bench setup through analysis, limit derivation and documented hand-off to validation.
• Characterize TX/RX Ser Des performance across process, voltage and temperature: swing, jitter, sensitivity, equalization, adaptation, CDR lock, BER bathtubs and shmoos.
• Own channel measurements to at least 50 GHz, including de-embedding, insertion/return loss, mixed-mode S-parameters and common-mode and mode-conversion behavior.
• Establish reference-paddle baselines and channel classes by gauge, reach and frequency; correlate HTDR-derived metrics with calibrated VNA measurements.
• Derive datasheet limits and guard-bands from measured distributions, accounting for uncertainty, sample coverage and aging; maintain traceable datasets and limit revisions.
• Assess carrier-loading and forwarded-clock tradeoffs using measured channel data and simulation, and translate the findings into supported configurations and characterization limits.
• Characterize power, energy per bit and thermal behavior across operating modes and corners; investigate equalizer noise amplification and channel/thermal interactions.
• Coordinate shared laboratory equipment and characterization milestones with validation teams; lead technical reviews and deliver limits in time for downstream qualification and screening.

• 10 to 14 years of experience in Ser Des/silicon characterization and/or high-speed channel and signal integrity characterization following degree completion.
• Direct ownership of a characterization program whose results became datasheet limits or qualification thresholds for a shipping product.
• Strong VNA measurement experience to 50 GHz or beyond, including de-embedding, mixed-mode S-parameters (Sdd/Scc/Scd/Sdc) and insertion/return-loss mask…