Senior IC Layout Engineer – FinFET

I am recruiting for a Senior IC Layout Engineer to join my client’s growing semiconductor team in Lausanne. The role offers hybrid working, with 3 days per week in the office.

The Senior IC Layout Engineer will be responsible for custom layout and physical verification of analog circuits, blocks and IP used in advanced high speed semiconductor designs, including multi Gigabit Ser Des and memory interfaces.

There is also scope to take ownership of wider chip layout activities and progress into a more senior technical position.

• Develop custom analog layouts for circuits, blocks and IP
• Work on high speed and high frequency circuits including amplifiers, PLLs, DLLs, oscillators, buffers, regulators and data converters
• Apply layout techniques for matching, parasitic reduction, power distribution and ESD
• Support full chip layout, integration and physical verification activities
• Perform DRC, LVS, parasitic extraction, EM and IR drop analysis
• Work with advanced process technologies including 28nm, 16nm and 7nm
• Use industry standard tools such as Cadence Virtuoso, Calibre and PVS

My client is looking for an experienced Analog IC Layout Engineer. High speed experience would be advantageous, but is not essential if you have strong experience with complex analog or high frequency designs.

The package includes a competitive salary, pension, private medical cover, visa sponsorship and relocation support where required.