Lead RTL Design Engineer Photonic Compute Path
Listed on 2026-10-11
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Engineering
Electronics Engineer, Hardware Engineer, Systems Engineer, Test Engineer
TRIA seeks a Senior RTL Design Engineer to lead RTL architecture and digital top-level integration for its photonic compute path. You will define the digital architecture, clock/reset strategy and interfaces, and write synthesizable RTL for control state machines and data paths.
Collaborate across photonics, analog, verification and layout teams through tapeout and first-silicon bring-up. 8+ years in ASIC RTL design with System Verilog, timing constraints and high-speed interfaces is required.
Our group is growing, and we are hiring a Lead RTL Design Engineer for Photonic Compute Path in Leeds, England, United Kingdom.
Join us at TRIA as our next Lead RTL Design Engineer for Photonic Compute Path in Leeds, England, United Kingdom.
We are currently recruiting a Lead RTL Design Engineer for Photonic Compute Path for our team in Leeds, England, United Kingdom.
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