Senior Engineer Digital Verification and Methodology

#We Are In  for jobs that impact everyone's life. Turning customer whispers into industry shaking solutions... ready to amplify the future?

As a Senior Engineer Digital Verification and Methodology on our Customer Collaboration and Technical Marketing team work hand-in-hand with our customers, enabling them to transform our products into cutting-edge designs, all while building long-lasting partnerships that thrive on success. Are you in? Your role Senior Engineer Digital Verification and Methodology:
Join a collaborative verification methodology team that delivers high-quality integrated circuits through scalable environments, robust planning and continuous improvement. You will own key verification capabilities and partner across disciplines to elevate productivity, quality, and reuse

• Create verification plans and translate requirements into test scenarios , checkers , assertions and measurable coverage goals
• Develop and maintain System Verilog and UVM environments, reusable components and verification IP
• Execute constrained random and directed verification of digital modules and analyze regressions and coverage
• Develop, deploy and maintain reusable verification methodologies , automation and workflow standards across projects
• Own selected methodology capabilities including requirements definition , implementation , documentation , user enablement and continuous improvement
• Evaluate and apply AI-based methodologies for verification planning , test generation , debug , coverage analysis and workflow automation
• Collaborate with concept , design and application engineering teams and internal customers to communicate technical risks and drive verification and methodology scope to completion

• Degree in Electrical Engineering , Computer Engineering , Computer Science or related field and strong knowledge of digital circuit theory and hardware description languages such as System Verilog
• Hands-on experience in digital IC verification using System Verilog and UVM including constrained random , coverage-driven verification , regressions and debug
• Programming or scripting in C , Python or Perl and strong Linux skills
• Ability to work independently and collaborate across teams with strong communication , with English level Written and Spoken Fluent

• Experience with formal verification , System Verilog assertions , firmware-driven verification or gate-level simulation
• Knowledge of microcontroller-based ICs , safety or security requirements or complex protocols
• Nice to have Experience improving and owning shared methodologies , enabling users , coordinating technical contributors or applying AI-based engineering approaches

Infineon Technologies is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, national origin, ancestry, citizenship, age, physical or mental disability, legally protected medical condition, family care status, military or veteran status, marital status, domestic partner status, sexual orientation, or any other basis protected by local, state, or federal laws.

Employment at Infineon is contingent upon proof of your legal right to work in the United States under applicable law, verification of satisfactory references, successful completion of a background check and drug test, and signing all your on-boarding documents. In some instances, if applicable, U.S. export control laws require that Infineon obtain a U.S. government export license prior to releasing technologies to certain persons.

This offer is contingent…