Senior Staff Engineer, Digital Verification and Methodology

#We Are In  for jobs that impact everyone's life.
Join the thinkers, builders, and problem solvers behind tomorrow’s technology.
As a Senior Staff Engineer, Digital Verification and Methodology on our Research &
Development team, you'll have the
opportunity to merge creativity with your
technical expertise by shaping the future of
technology, driving groundbreaking projects,
and bringing new ideas to life.
Are you in?

Your role Senior
Staff Engineer, Digital Verification and Methodology. Join a collaborative team
that values diverse perspectives and leads functional verification for advanced
integrated circuits while scaling reusable methodologies across global
development sites

Key responsibilities in your new role

Lead end-to-end verification
strategy from requirements analysis through sign-off Architect reusable System Verilog
UVM environments and scalable object-oriented test benches

Implement constrained-random
and assertion-based verification with robust functional coverage

Drive metric-driven coverage
closure and establish clear quality criteria

Translate specifications
and microarchitecture into tests, checkers, coverage
models, and sign-off evidence

Improve verification methodologies,
automation, and tool flows across projects and development sites

Collaborate with design, firmware,
and system teams to debug issues and ensure reliable hardware-software
interaction

Your profile You
bring analytical thinking, clear communication, and collaborative problem-solving.
You thrive in a globally distributed environment and build trust across
functions while driving results

Qualifications and skills to help you succeed Mandatory:
Bachelor’s or
master’s degree in electrical engineering, Computer Engineering, Computer
Science, or a related technical field

Mandatory: 5+ years in ASIC,
SoC, or FPGA functional verification with ownership of complex block,
subsystem, or chip-level deliverables

Mandatory:
Expert proficiency in System Verilog,
UVM, object-oriented testbench architecture, constrained-random
verification, functional coverage, and assertion-based
verification

Mandatory:
Ability to translate specifications
and microarchitecture into verification plans, environments,
tests, checkers, coverage models, and sign-off evidence

Mandatory:
Written and spoken English
at C1 level

Preferred:
Strong debugging
skills with a major simulation and debug toolchain and proficiency in Linux
development and scripting or programming with Python, Tcl,
Bash, C, or C++ for automation

Nice-to-have:

Experience with RTL
design and digital architecture plus exposure to Ethernet or
complex protocols, security verification for cryptographic
accelerators or secure subsystems, power-aware verification using UPF,
and practical use of AI or machine learning and AI-enabled EDA
tools

Additional information

Infineon Technologies is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, national origin, ancestry, citizenship, age, physical or mental disability, legally protected medical condition, family care status, military or veteran status, marital status, domestic partner status, sexual orientation, or any other basis protected by local, state, or federal laws.

Employment at Infineon is contingent upon proof of your legal right to work in the United States under applicable law, verification of satisfactory references, successful completion of a background check and drug test, and signing all your on-boarding  some instances, if applicable, U.S. export control laws require that Infineon obtain a U.S. government export license prior to releasing technologies to certain persons.

This offer is contingent…