Senior SerDes Clocking Architect — Ultra-Low Jitter PLLs
Listed on 2026-11-05
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Engineering
Systems Engineer, Hardware Engineer
Upscale, Inc. is building high‑performance AI infrastructure and seeking a senior Ser Des clocking leader to define the clocking architecture for next‑gen Ser Des in 5nm and below.
You will own PLL design, latency, and jitter performance, coordinating across analog, mixed‑signal, digital, and layout teams to ensure robust, power‑efficient clocking solutions and successful silicon delivery.
The Senior Ser Des Clocking Architect — Ultra-Low Jitter PLLs role at Upscale, Inc. is now open for applications in KY, United States.
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This posting is for the Senior Ser Des Clocking Architect — Ultra-Low Jitter PLLs role at Upscale, Inc., based in KY, United States.
We are looking to fill the Senior Ser Des Clocking Architect — Ultra-Low Jitter PLLs position at Upscale, Inc. in KY, United States.
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