Principal​/Senior Principal FPGA​/ASIC Verification Engineer

Overview

RELOCATION ASSISTANCE:
Relocation assistance may be available. CLEARANCE TYPE:
Polygraph. TRAVEL:
Yes, 10% of the Time.

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people’s lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation’s history — from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon.

We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they’re making history.

Join Northrop Grumman on our continued mission to push the boundaries of possible across land, sea, air, space, and cyberspace. Enjoy a culture where your voice is valued and start contributing to our team of passionate professionals providing real-life solutions to our world’s biggest challenges. We take pride in creating purposeful work and allowing our employees to grow and achieve their goals every day by Defining Possible.

With our competitive pay and comprehensive benefits, we have the right opportunities to fit your life and launch your career today.

Northrop Grumman Mission Systems Sector (NGMS) is a leading global provider of secure software-defined, hardware enabled mission systems. Our company is pioneering capabilities in a wide variety of sectors that keep our nation and our allies safe from undersea to space and cyberspace.

We are seeking digital verification engineers for our development of full-custom digital and mixed signal circuits. Responsibilities include contributing to verification planning and execution for HDL (VHDL/Verilog) and HVL (System Verilog), using System Verilog Assertions (SVA) and Universal Verification Methodology (UVM), and applying a coverage-driven verification methodology from planning through closure. Strong collaboration with teams and effective communication are expected.

Basic qualifications – Principal Digital Verification Engineer:

• Bachelor’s degree in a technical area (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with technical MS; 0 years with PhD) – Experience in HDL (VHDL/Verilog) and HVL (System Verilog)
• Experience with FPGA or ASIC
• Knowledge of Universal Verification Methodology (UVM)
• Experience with scripting languages (Bash, Perl, Python, Tcl)
• Familiarity with Linux OS
• Familiarity with a coverage driven verification methodology from planning through closure
• Knowledge of industry standard interfaces
• Experience with object-oriented programming languages and concepts
• Must be a US Citizen and must have or be able to obtain and maintain a Top Secret/SCI security clearance with Polygraph

Basic qualifications – Senior Principal Digital Verification Engineer:

• Bachelor’s degree in a technical area (BSEE or other Engineering discipline preferred) with 8 years of relevant experience (6 years with technical MS; 3 years with PhD) – Experience in HDL (VHDL/Verilog) and HVL (System Verilog)
• Experience with FPGA or ASIC
• Knowledge of Universal Verification Methodology (UVM)
• Experience with scripting languages (Bash, Perl, Python, Tcl)
• Familiarity with Linux OS
• Familiarity with a coverage driven verification methodology from planning through closure
• Knowledge of industry standard interfaces
• Experience with object-oriented programming languages and concepts
• Must be a US Citizen and must have or be able to obtain and maintain a Top Secret/SCI security clearance with Polygraph

Preferred qualifications – Principal / Senior Principal Digital Verification Engineer:

• Advanced Degree either MS or PhD
• Active Top Secret/SCI security clearance with Polygraph
• Experience with Mentor Graphics and/or Cadence Verification tools – FPGA/ASIC design experience

Northrop Grumman provides a comprehensive benefits package and…