Senior Design Verification Engineer

A leading global technology firm is seeking a Senior
Design Verification Engineer to work on high-performance FPGA and ASIC systems used in ultra-low-latency, real-time environments. This role focuses on building robust verification frameworks to ensure the correctness, reliability, and performance of complex hardware designs.

You’ll design and own verification environments, work closely with RTL designers on rapid bring-up and debugging, and contribute to both internal and open-source tooling
. The team values engineers who are not only strong verifiers but also enjoy improving tools, workflows, and the broader EDA ecosystem. No domain-specific (e.g., finance) experience is required.

• Develop test benches, tests, and verification environments for FPGA/ASIC designs
• Create and maintain detailed verification plans
• Debug and root-cause complex RTL issues
• Collaborate closely with hardware designers on new and existing projects
• Manage test suites, coverage, and CI infrastructure
• Contribute to internal tools and open-source verification projects

• 2+ years’ experience in FPGA or ASIC functional verification
• Strong System Verilog skills (UVM or similar frameworks)
• Experience with functional and code coverage
• Proficiency in Python
  ; C++ a plus
• Comfortable working in a Linux environment
• Familiarity with Verilator and/or Cocotb is advantageous
• Degree in Electrical Engineering, Computer Science, or related field