Design Verification Engineer

I am seeking a Senior Verification Engineer to join an established and fast-growing startup as it enters its next phase of growth. With a team of nearly 100 people, this company is at the forefront of post-quantum cryptography
, developing security-critical technologies with global impact.

You will play a key role in verifying highly secure designs, working closely with experienced engineers in a collaborative, high-trust environment.

As part of the verification team, you will:

• Build and extend UVM test benches to verify cryptographic IP and subsystem designs
• Develop Python-based tools and automation to improve verification efficiency and productivity
• Apply formal verification techniques in creative and effective ways

• Influence and define verification methodologies and strategies
• Architect test benches using UVM and formal-based approaches
• Define verification plans, functional coverage models, and test strategies at block and subsystem level
• Lead verification for IPs or subsystems, including effort estimation, scheduling, task allocation, and progress reporting
• Drive coverage closure and sign-off quality across complex designs
• Mentor junior engineers and help raise the overall capability of the team

• Strong background in UVM-based verification at IP and subsystem levels
• Proven experience building UVM test benches from scratch
• Proficiency in Python for verification automation
• Solid experience with System Verilog Assertions (SVA)
• A minimum of 4 years experience.

• Competitive base salary plus share options
• Opportunity to help build something from the ground up in a growing, mission-driven company
• Fully remote role (must be based at a UK address)

This role will suit someone who thrives in small, collaborative teams
, communicates clearly, and is passionate about delivering high-quality verification for security-critical systems.