Formal Verification Engineer

Description

As a formal verification architect leading the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for:

• Working with Apple's world-class design engineers to develop a formal micro-architecture specification.
• Formalizing the refinement from architecture to micro‑architecture.
• Developing a comprehensive formal verification test plan.
• Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro‑architecture.
• Crafting novel and creative solutions for verifying complex design micro‑architectures.
• Developing and implementing reusable and optimised formal models and verification code base.
• Architecting correct‑by‑construction design methodologies for improved formal verification efficiency and productivity.

• Hands‑on experience with VLSI and digital logic design and verification techniques
• Advanced knowledge of SoC, CPU, GPU, or Cellular designs
• Developed formal property proofs on industrial strength designs and architectures
• Deep understanding of pipeline architectures, memory/DMA controllers, out‑of‑order and speculative instruction execution hardware, bus interconnects, and cache coherence mechanisms
• Confirmed understanding of formal verification technologies/abstraction techniques
• Knowledge and experience in interpreting hardware specifications and using
• Temporal logic assertion‑based languages such as SVA or PSL
• Experience in using EDA formal tools and tool development experience is a plus
• Proficiency in any scripting language with excellent debugging skills
• Extraordinary teammate with excellent interpersonal skills
• Passionate about developing world‑class/innovative formal verification solutions
• Understanding of application processors (CPU/GPU), their Instruction Set Architectures (ISA), Memory Consistency Models (MCM) or Cache Coherence protocols is desirable but not necessary
• Exposure to ARM type architectures is desirable but not necessary

• Knowledge and experience in interpreting hardware specifications and using
• Temporal logic assertion‑based languages such as SVA or PSL
• BS / MS / Ph.D in EE or CS is required.

We are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law.