Front-End Implementation; Synthesis Engineer

Summary

Join the GPU Front End Implementation team, responsible for crafting and building world‑class GPUs that power Apple Silicon.

Candidates will be responsible for PPA optimisation of the netlist, working collaboratively with RTL and Physical design teams. Delivery of key netlist quality milestones and improvement of current methodologies is expected.

• Minimum of BSc in EE.
• Proficient in Verilog and/or System Verilog and scripting languages.
• Experience with physical synthesis, including logic and PPA optimisation techniques.

• Understanding and application of physical design and static timing analysis principles.
• Familiarity with DFT insertion.
• Familiarity with reset domain, multi‑clock domain, multi‑power domain (UPF), linting tools and concepts across RTL and Gate‑Level.
• Experience implementing ECO's for functionality and timing.
• Ability to analyze critical paths and guide RTL designs to efficient solutions.
• Experience using logic equivalence tools for RTL and Gate‑level designs.
• Collaboration with IP teams across multiple sites.

At Apple, we are committed to treating all applicants fairly and equally. We will work with applicants to make reasonable accommodations. Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. We believe accessibility is a fundamental right and we aim to build a career where everyone feels they belong.