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Verification Engineer

Job in Greater London, London, Greater London, W1B, England, UK
Listing for: Oriole
Full Time position
Listed on 2026-07-14
Job specializations:
  • Engineering
    Test Engineer
Salary/Wage Range or Industry Benchmark: 65000 - 95000 GBP Yearly GBP 65000.00 95000.00 YEAR
Job Description & How to Apply Below
Location: Greater London

At Oriole Networks, we are developing disruptive technologies for AI/ML and HPC networking that will revolutionise Data Centers. These technologies will speed up training and inference while dramatically reducing energy consumption for a sustainable future.

We are looking for an experienced Verification Engineer to work within our existing team to develop high-speed network interfaces between xPUs and our proprietary network. The successful candidate will deliver module and system level verification solutions, working iteratively through a series of prototypes to ultimately deliver a production‑grade solution. Responsibilities will include verification infrastructure architecting, verification planning, testbench and test implementation, and coverage closure.

Responsibilities:
  • Definition and execution of verification strategies and plans based on specification and collaboration with the broader team
  • Develop test benches at module and system level, including stimulus, monitors, checkers, and scoreboards
  • Develop tests, maintain functional coverage models and drive coverage closure
  • Support hardware validation, reproducing and debugging complex functional issues, working closely with RTL and system teams, to resolve root causes
Skills & Experience:
  • Extensive hands‑on industry experience of FPGA or ASIC verification, ideally for GPU/CPU interfacing and networking at 100

    Gbps and above
  • Experience verifying at unit and system level, particularly for FPGA solutions, ideally for production quality IP
  • Experience architecting verification environments and infrastructure
  • Strong knowledge of verification methodologies, functional coverage, assertions and constrained random verification
  • Excellent skills in System Verilog
  • Scripting and automation, such as TCL and Python
  • Experience using Questa, VCS
  • Experience of formal verification tools, for example Questa Formal, Jasper Gold
  • Experience of many of the following: UALink, NVLink, PCIe, RDMA, CXL
  • A humble attitude and good communication skills
  • Bachelor or Master degree in electronics engineering, physics, or other relevant fields or experience within the industry;
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