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Systems Engineer, Digital Payload

Job in Greater London, London, Greater London, W1B, England, UK
Listing for: Viasat
Full Time position
Listed on 2026-08-29
Job specializations:
  • Engineering
    Systems Engineer, Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 90000 - 130000 GBP Yearly GBP 90000.00 130000.00 YEAR
Job Description & How to Apply Below
Location: Greater London

About us

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.

What

you'll do

We are seeking an experienced Digital Payload Systems Engineer to provide technical leadership for complex digital space systems. This role owns end-to-end digital payload architecture, system performance, requirements, technical budgets, verification strategy, and long-term payload evolution.

The successful candidate will serve as a senior technical authority across FPGA and ASIC based digital systems, independently defining complex problems, driving architecture decisions, coordinating cross-functional execution, and mentoring other engineers. This role requires deep subject matter expertise, strong systems judgment, and the ability to influence technical outcomes across programs without direct authority.

The day-to-day
  • Own end-to-end digital payload system performance, architecture, requirements, and verification strategy.
  • Lead architecture definition and trade studies for FPGA, ASIC, DSP, high-speed I/O, clocking, and payload processing systems.
  • Define and resolve complex system-level problems across hardware, firmware, software, RF, integration, and test teams.
  • Drive design decisions for beamforming, channelization, regenerative payloads, and standards-based implementations including DVB-S2, DVB-S2X, DVB-RCS, and 3

    GPP.
  • Own technical budgets, margin posture, assumptions, risks, and analytical models supporting program decisions.
  • Develop and maintain key technical artifacts, including SRDs, TRDs, interface specifications, trade studies, and verification plans.
  • Lead requirements decomposition, allocation, traceability, and burndown across subsystem teams.
  • Support major lifecycle reviews including SRR, PDR, CDR, test readiness, and operational readiness reviews.
  • Define system-level verification and validation strategies with integration and test teams.
  • Provide technical leadership on interfaces, timing, throughput, resource utilization, high-speed data movement, and payload processing behavior.
  • Communicate technical recommendations, risks, and tradeoffs to engineering and program leadership.
  • Mentor engineers and help improve systems engineering practices, standards, and digital payload development processes.
What you'll need
  • Bachelor’s degree in Engineering, Physics, Computer Engineering, Electrical Engineering, or related technical field, or equivalent experience.
  • 8+ years of relevant experience in systems engineering, digital payload development, FPGA or ASIC based systems, aerospace, space, or mission-critical systems.
  • Demonstrated ability to independently define ambiguous technical problems, select appropriate methods, and drive resolution across teams.
  • Proven experience owning payload or system-level technical budgets for performance, latency, throughput, power, timing, resources, margin, and risk.
  • Deep experience with requirements development, decomposition, allocation, traceability, and verification closure.
  • Strong understanding of full lifecycle systems engineering from concept definition through integration, verification, and operational readiness.
  • Significant FPGA and ASIC architecture or implementation experience.
  • Strong technical foundation in DSP, communication systems, high-speed digital interfaces, and payload data path architecture.
  • Proficiency with VHDL, Verilog, System Verilog, or equivalent hardware description languages.
  • Deep understanding of SERDES, transceivers, clocking architectures, synchronization, timing closure, high-speed link bring-up, and lab debugging.
  • Ability to influence technical outcomes across multidisciplinary teams without direct authority.
  • Strong communication skills for senior-level design reviews, risk discussions, and technical decision forums.
  • Experience mentoring engineers and improving technical practices across a team or organization.
What…
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