Senior FPGA Developer – Leading Algo Trading Firm

Senior FPGA Developer – Low latency hardware design

Global Quantitative Trading Firm – Industry leading compensation London – Hybrid (4 days onsite / 1 remote)
Quant Capital is hiring on behalf of a leading trading firm that is building a new specialist FPGA engineering team. This is a greenfield opportunity to design and deliver high-performance hardware platforms used in latency-critical environments. The team is being established to take full ownership of FPGA development previously handled across other functions.

This role is ideal for an FPGA engineer who can move beyond textbook RTL, write hardware-aware designs, and has strong instincts around speed, area, and resource optimisation.

Role Overview You’ll be working on complex, high-throughput designs deployed to large FPGAs. Expect to handle fast I/O (Ethernet, PCIe, external memory), deep pipelines, and high-density logic. The team uses Verilog/System Verilog, leverages Cocotb/Verilator for testing, and applies formal methods selectively. You’ll collaborate closely with software and ASIC teams to extend existing platforms and deliver new high-impact projects.

This role offers scope for ownership from day one, with a long-term roadmap and autonomy over architecture, implementation, and methodology.

Key Responsibilities Design high-performance, resource-efficient FPGA architectures

Work on projects involving high-speed interfaces (PCIe, Ethernet, etc.) and external memory

Translate high-level functional specs into structured RTL with synthesis in mind Collaborate with ASIC and software teams on integrated platform development

Contribute to internal tooling and methodology refinement

Build test benches and validation flows (Cocotb, Verilator); apply formal methods where needed

What You’ll Need Deep experience in Verilog or System Verilog Strong  understanding of FPGA internals and how to structure hardware to target them effectively

Experience working on large-scale designs (high throughput, multiple clock domains, deep pipelines)
Familiar with high-speed serial interfaces (e.g. Ethernet, USB 3.1, Fibre Channel)
Practical experience balancing timing closure, area, and power trade-offs Familiarity with test and verification methodologies (Cocotb preferred)
Nice to Have

Experience with low-latency applications or trading environments

Exposure to formal verification tools

Comfort working in small, agile engineering teams with broad ownership

Why Apply?

Shape the foundation of a new FPGA function in a high-impact environment

Work on meaningful, deeply technical projects with long-term scope

Collaborate with elite teams across software and silicon

Join a business where engineering drives product and results

Clean code, smart hardware, and real ownership from day oneAll applications are handled in strict confidence – your profile will never be shared without your consent.