Avionics FPGA Engineer United Kingdom

Lodestar's mission is to develop the first "Protect and Defend" capability for high-value space assets in orbit. Our flagship product, MITHRIL, is our hardware-agnostic, AI-enabled autonomy software suite that enables us to augment any off-the-shelf spacecraft with the ability to autonomously detect, characterise, and reversibly neutralise orbital threats. By building on the proven space heritage of our best-in-class satellite-bus partners and fully integrating MITHRIL into a single unified platform, we deliver an end-to-end, autonomous in-space bodyguarding service.

We are seeking a highly motivated Avionics FPGA Engineer to join our multidisciplinary team developing next-generation space systems. You will be responsible for designing, implementing, and validating advanced avionics architectures for autonomous platforms. This role offers the opportunity to work hands-on across the full lifecycle, from concept and simulation to hardware testing and on-orbit readiness.

• Design, develop, and verify RTL in System Verilog and/or Verilog for FPGA and SoC targets.
• Bring up and integrate Ser Des interfaces and memory interfaces.
• Develop test benches and formal proofs to ensure module and system level correctness
• Conduct hardware debugging and system level testing using oscilloscopes, logic analysers, and other lab instrumentation.
• Collaborate closely with systems, avionics software and hardware teams to ensure seamless integration of RTL designs into flight systems.
• Contribute to design documentation, test plans, and the evidence needed for design reviews, and support environmental qualification and verification testing (EMC, vibration, thermal vacuum, etc.)

• BEng / MEng in Electrical Engineering, a related field, or equivalent experience.
• Proficiency in System Verilog and/or Verilog, with a solid grasp of RTL design principles.
• Hands-on experience with at least one FPGA family or ecosystem
• Familiarity with common digital interfaces and protocols (SPI, I2C, UART)
• Experience with simulation and formal verification
• Experience dealing with clock domain crossings, static timing analysis and timing closure.
• Comfort scripting for automation, ideally in Python and/or TCL.
• Hands on experience with lab test equipment including oscilloscopes, logic analysers, and power supplies.
• Clear communication and a proactive, curious approach to picking up new tools and ideas.

• High speed interfaces: MIPI-CSI, QSGMII, SGMII, 10
  
  GBASE-KR, PCIe or similar.
• Memory interfaces: DDR3, DDR4, LPDDR4 or similar
• SoC design: integrating RISC-V or Arm processor subsystems, AXI/APB/AHB protocols, and embedded Linux bring-up.
• Experience with PCB design for high speed digital designs.
• Strong knowledge of verification methodologies, functional coverage, assertions and constrained random verification
• Experience with Microchip FPGAs and development tools.
• Background in space rated electronics and high reliability design practices, including radiation effects analysis, fault tolerant architectures, and qualification processes for space systems.
• Time-Sensitive Networking (TSN) or other deterministic networking.
• Pay Range:
  • (E1) Junior Engineer: £30,000 - £55,000 / year
  • (E2) Mid-level Engineer: £55,000 - £75,000 / year
• Meaningful equity incentives as part of our employee option pool
• Contributory pension
• Be part of a scrappy, dynamic, multidisciplinary, collaborative crew

For security reasons background checks will be undertaken prior to any employment offers being made to an applicant. These checks will include nationality checks as it is a requirement of this position that you be eligible to access equipment and data regulated by the United States' International Traffic in Arms Regulations.

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