Senior ASIC Verification Engineer: SystemVerilog/UVM, UPF
Listed on 2026-10-11
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Engineering
Test Engineer
Swedium Global Services is seeking an experienced ASIC Verification Engineer to join our growing verification team. You will lead System Verilog/UVM based verification, develop test plans, and verify UPF-powered features for complex ASIC/SoC designs.
Remote from EU position with 8+ years of related experience; strong debugging and collaboration with design teams are essential for timely verification closure and regression testing.
We are currently recruiting a Senior ASIC Verification Engineer:
System Verilog/UVM, UPF for our team in Greater London, England, United Kingdom.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior ASIC Verification Engineer:
System Verilog/UVM, UPF role in the description above.
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